Fault tolerance estimation in digital circuits with visualised generative networks 事件

Fault tolerance estimation in digital circuits with visualised generative networks arXiv:2605.15212v2 Announce Type: replace-cross Abstract: We propose a new numerical method to estimate the fault tolerance of failure modes in digital circuit structures with a generative network sampling technique. From a random input of generated bitwise configurations of ideally digitalised analog currents in the digital circuit design with classical logical gates, expected output currents are compared to the