Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs 论文

2006Proceedings/Proceedings - International Test Conference引用 239
DOI
VLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure AnalysisPhysical Unclonable Functions (PUFs) and Hardware Security
VLSI and Analog Circuit TestingPhysical Unclonable Functions (PUFs) and Hardware SecurityIntegrated Circuits and Semiconductor Failure Analysis
关系图谱

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs · 相关文章

暂无数据