VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification 事件

VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification arXiv:2603.11075v3 Announce Type: replace-cross Abstract: As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-base