AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications 事件

AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications arXiv:2605.27472v1 Announce Type: cross Abstract: Assertion-based verification (ABV) is a cornerstone of modern hardware design, yet manually translating design intent into formal SystemVerilog Assertions (SVAs) remains labor-intensive and error-prone. While Large Language Models (LLMs) show promise for automating this process, existing benchmarks remain limited by unrealistic task formulations, weak s