Geometry-Aware Probabilistic Circuits via Voronoi Tessellations 事件

Geometry-Aware Probabilistic Circuits via Voronoi Tessellations arXiv:2603.11946v2 Announce Type: replace-cross Abstract: Probabilistic circuits (PCs) enable exact and tractable inference but employ data independent mixture weights that limit their ability to capture local geometry of the data manifold. We propose Voronoi tessellations (VT) as a natural way to incorporate geometric structure directly into the sum nodes of a PC. However, na\"ively introducing such structure breaks tractability.