A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA 论文

2004引用 218
DOI
Cryptographic Implementations and SecurityChaos-based Image/Signal EncryptionCoding theory and cryptography
Coding theory and cryptographyChaos-based Image/Signal EncryptionCryptographic Implementations and Security
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A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA · 作者

I

Ingrid Verbauwhede

A

A. Hodjat