First-Order Incremental Block-Based Statistical Timing Analysis 论文

2006IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems引用 231
DOI
VLSI and FPGA Design TechniquesLow-power high-performance VLSI designVLSI and Analog Circuit Testing
VLSI and FPGA Design TechniquesLow-power high-performance VLSI designVLSI and Analog Circuit Testing
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First-Order Incremental Block-Based Statistical Timing Analysis · 相关技术

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