Exploiting symmetry in temporal logic model checking 论文

1996Formal Methods in System Design引用 321
DOI
Formal Methods in VerificationRadiation Effects in ElectronicsEmbedded Systems Design Techniques
Formal Methods in VerificationEmbedded Systems Design TechniquesRadiation Effects in Electronics
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Somesh Jha

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Thomas Filkorn

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Reinhard Enders

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E. M. Clarke

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Formal Methods in Verification

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