Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS 论文
2007引用 235
VLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure AnalysisAdvancements in Semiconductor Devices and Circuit Design
详细信息
- 发表日期
- 2007-01-01
- 发表年份
- 2007
关键词
VLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure AnalysisAdvancements in Semiconductor Devices and Circuit Design
摘要
This paper presents an overview of process variation effects, including examples of mitigation strategies and test methods. Experimental and theoretical comparisons are presented for 45 nm and 65 nm RDF. SRAM matching and interconnect variation is discussed for both 65 nm and 45 nm, including examples of process and design mitigation strategies. Use of ring oscillators for detailed measurement of within-wafer and within-die variation is illustrated for 65 nm and 45 nm products.