A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling 论文

2002IEEE Journal of Solid-State Circuits引用 215
Low-power high-performance VLSI designParallel Computing and Optimization TechniquesAnalog and Mixed-Signal Circuit Design

详细信息

发表期刊/会议
IEEE Journal of Solid-State Circuits
发表日期
2002-11-01
发表年份
2002

关键词

Low-power high-performance VLSI designParallel Computing and Optimization TechniquesAnalog and Mixed-Signal Circuit Design

摘要

A PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described. The PowerPC core and caches achieve frequencies as high as 380 MHz at a supply of 1.8 V and active power consumption as low as 53 mW at a supply of 1.0 V. The system executes up to 500 MIPS and can achieve standby power as low as 54 /spl mu/W. Logic supply changes as fast as 10 mV//spl mu/s are supported. A low-voltage PLL supplied by an on-chip regulator, which isolates the clock generator from the variable logic supply, allows the SOC to operate continuously while the logic supply voltage is modified. Hardware accelerators for speech recognition, instruction-stream decompression and cryptography are included in the SOC. The SOC occupies 36 mm/sup 2/ in a 0.18 /spl mu/m, 1.8 V nominal supply, bulk CMOS process.