A two-step genetic algorithm for mapping task graphs to a network on chip architecture 论文

2003引用 264
DOI
Interconnection Networks and SystemsEmbedded Systems Design TechniquesParallel Computing and Optimization Techniques
Parallel Computing and Optimization TechniquesEmbedded Systems Design TechniquesInterconnection Networks and Systems
相关技术:Interconnection Networks and SystemsParallel Computing and Optimization Techniques
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