ORION 2.0: A Power-Area Simulator for Interconnection Networks 论文
2011IEEE Transactions on Very Large Scale Integration (VLSI) Systems引用 253
Interconnection Networks and SystemsParallel Computing and Optimization TechniquesLow-power high-performance VLSI design
详细信息
- 发表期刊/会议
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- 发表日期
- 2011-03-15
- 发表年份
- 2011
关键词
Interconnection Networks and SystemsParallel Computing and Optimization TechniquesLow-power high-performance VLSI design
摘要
As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. In this work, we present ORION 2.0, an enhanced NoC power and area simulator, which offers significant accuracy improvement relative to its predecessor, ORION 1.0.