A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures 论文

1993IEEE Transactions on Parallel and Distributed Systems引用 886

Interconnection Networks and SystemsEmbedded Systems Design TechniquesParallel Computing and Optimization Techniques

Parallel Computing and Optimization Techniques Embedded Systems Design Techniques Interconnection Networks and Systems

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The authors present a compile-time scheduling heuristic called dynamic level scheduling, which accounts for interprocessor communication overhead when mapping precedence-constrained, communicating tasks onto heterogeneous processor architectures with limited or possibly irregular interconnection structures. This technique uses dynamically-changing priorities to match tasks with processors at each step, and schedules over both spatial and temporal dimensions to eliminate shared resource contention. This method is fast, flexible, widely targetable, and displays promising performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

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Edward A. Lee

G.C. Sih

A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures 论文

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