A Read-Static-Noise-Margin-Free SRAM Cell for Low-VDD and High-Speed Applications 论文
2005IEEE Journal of Solid-State Circuits引用 294
Low-power high-performance VLSI designVLSI and Analog Circuit TestingVLSI and FPGA Design Techniques
摘要
To help overcome limits to the speed of conventional SRAMs, we have developed a read-static-noise-margin-free SRAM cell. It consists of seven transistors, several of which are low-Vth nMOS transistors used to achieve both low-VDD and high-speed operations. For the same speed, the area of our proposed SRAM is 23% smaller than that of a conventional SRAM. Further, we have fabricated a 64-kb SRAM macro using 90-nm CMOS technology and have obtained with it a minimum VDD of 440 mV and a 20-ns access time with a 0.5-V supply.