Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations 论文

2003引用 398
DOI
Low-power high-performance VLSI designVLSI and Analog Circuit TestingVLSI and FPGA Design Techniques
VLSI and FPGA Design TechniquesLow-power high-performance VLSI designVLSI and Analog Circuit Testing
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Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations · 作者

V

Vladimir Zolotov

D

David Blaauw

A

Aseem Agarwal