The TimberWolf placement and routing package 论文

1985IEEE Journal of Solid-State Circuits引用 534
VLSI and FPGA Design TechniquesVLSI and Analog Circuit Testing3D IC and TSV technologies

摘要

TimberWolf is an integrated set of placement and routing optimization programs. The general combinatorial optimization technique known as simulated annealing is used by each program. Programs for standard cell, macro/custom cell, and gate-array placement, as well as standard cell global routing, have been developed. Experimental results on industrial circuits show that area savings over existing layout programs ranging from 15 to 62% are possible.

相关技术

暂无数据

相关事件

暂无数据

相关文章

暂无数据