A semidigital dual delay-locked loop 论文

1997IEEE Journal of Solid-State Circuits引用 337
DOI
Advancements in PLL and VCO TechnologiesAnalog and Mixed-Signal Circuit DesignVLSI and Analog Circuit Testing
VLSI and Analog Circuit TestingAdvancements in PLL and VCO TechnologiesAnalog and Mixed-Signal Circuit Design
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A semidigital dual delay-locked loop · 相关技术

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