Survey of Test Vector Compression Techniques 论文
2006IEEE Design & Test of Computers引用 440
VLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure AnalysisEngineering and Test Systems
详细信息
- 发表期刊/会议
- IEEE Design & Test of Computers
- 发表日期
- 2006-04-01
- 发表年份
- 2006
关键词
VLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure AnalysisEngineering and Test Systems
摘要
Test data compression consists of test vector compression on the input side and response, compaction on the output side. This vector compression has been an active area of research. This article summarizes and categories these techniques. The focus is on hardware-based test vector compression techniques for scan architectures. Test vector compression schemes fall broadly into three categories: code-based schemes use data compression codes to encode test cubes; linear-decompression-based schemes decompress the data using only linear operations (that is LFSRs and XOR networks) and broadcast-scan-based schemes rely on broadcasting the same values to multiple scan chains