Clock-gating and its application to low power design of sequential circuits 论文
2000IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications引用 253
Low-power high-performance VLSI designVLSI and FPGA Design TechniquesVLSI and Analog Circuit Testing
摘要
This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and analyze two clock-gating techniques. It then uses the covering relationship between the triggering transition of the clock and the active cycles of various flip flops to generate a derived clock for each flip flop in the circuit. A technique for clock gating is also presented, which generates a derived clock synchronous with the master clock. Design examples using gated clocks are provided next. Experimental results show that these designs have ideal logic functionality with lower power dissipation compared to traditional designs.