Secure Scan: A Design-for-Test Architecture for Crypto Chips 论文

2006IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems引用 238
DOI
Physical Unclonable Functions (PUFs) and Hardware SecurityVLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure Analysis
VLSI and Analog Circuit TestingPhysical Unclonable Functions (PUFs) and Hardware SecurityIntegrated Circuits and Semiconductor Failure Analysis
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Secure Scan: A Design-for-Test Architecture for Crypto Chips · 作者

B

Bo Yang

R

Ramesh Karri

K

Kaijie Wu