GARNET: A detailed on-chip network model inside a full-system simulator 论文

2009引用 753
DOI
Interconnection Networks and SystemsParallel Computing and Optimization TechniquesEmbedded Systems Design Techniques
Parallel Computing and Optimization TechniquesEmbedded Systems Design TechniquesInterconnection Networks and Systems
相关技术:Parallel Computing and Optimization TechniquesInterconnection Networks and Systems
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GARNET: A detailed on-chip network model inside a full-system simulator · 作者

N

Niraj K. Jha

L

Li-Shiuan Peh

T

Tushar Krishna

N

Niket Agarwal