Tiered-latency DRAM: A low latency and low cost DRAM architecture 论文

2013引用 263
DOI
Parallel Computing and Optimization TechniquesAdvanced Memory and Neural ComputingFerroelectric and Negative Capacitance Devices
Parallel Computing and Optimization TechniquesAdvanced Memory and Neural ComputingFerroelectric and Negative Capacitance Devices
相关技术:Advanced Memory and Neural ComputingParallel Computing and Optimization Techniques
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Tiered-latency DRAM: A low latency and low cost DRAM architecture · 相关技术

相关技术

Advanced Memory and Neural ComputingParallel Computing and Optimization Techniques