Buffer placement in distributed RC-tree networks for minimal Elmore delay 论文

2002引用 564
DOI
Low-power high-performance VLSI designVLSI and Analog Circuit TestingInterconnection Networks and Systems
Low-power high-performance VLSI designVLSI and Analog Circuit TestingInterconnection Networks and Systems
相关技术:Interconnection Networks and Systems
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Buffer placement in distributed RC-tree networks for minimal Elmore delay · 相关事件

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