Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip 论文

2002Journal of Electronic Testing引用 404
DOI
VLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure AnalysisVLSI and FPGA Design Techniques
半导体VLSI and FPGA Design TechniquesVLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure Analysis
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E

Erik Jan Marinissen

K

Krishnendu Chakrabarty

V

Vikram Iyengar

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