A reduced clock-swing flip-flop (RCSFF) for 63% power reduction 论文

1998IEEE Journal of Solid-State Circuits引用 266
DOI
Low-power high-performance VLSI designQuantum-Dot Cellular AutomataAnalog and Mixed-Signal Circuit Design
Low-power high-performance VLSI designQuantum-Dot Cellular AutomataAnalog and Mixed-Signal Circuit Design
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A reduced clock-swing flip-flop (RCSFF) for 63% power reduction · 作者

T

T. Sakurai

H

Hiroshi Kawaguchi