Compiler validation via equivalence modulo inputs 论文

2014引用 370
DOI
Software Testing and Debugging TechniquesFormal Methods in VerificationSoftware Reliability and Analysis Research
Formal Methods in VerificationSoftware Testing and Debugging TechniquesSoftware Reliability and Analysis Research
相关技术:Formal Methods in Verification
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Compiler validation via equivalence modulo inputs · 相关技术

相关技术

Formal Methods in Verification