A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors 论文

2018引用 242
DOI
Advanced Memory and Neural ComputingFerroelectric and Negative Capacitance DevicesAdvanced Neural Network Applications
人工智能Advanced Neural Network ApplicationsAdvanced Memory and Neural ComputingFerroelectric and Negative Capacitance Devices
相关技术:Advanced Neural Network ApplicationsAdvanced Memory and Neural Computing
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A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors · 相关文章

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