Gated-V/sub dd/: a circuit technique to reduce leakage in deep-submicron cache memories 论文

2000ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)引用 267
DOI
Low-power high-performance VLSI designParallel Computing and Optimization TechniquesAdvanced Memory and Neural Computing
Parallel Computing and Optimization TechniquesAdvanced Memory and Neural ComputingLow-power high-performance VLSI design
相关技术:Advanced Memory and Neural ComputingParallel Computing and Optimization Techniques
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