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It designs, manufactures, and sells computer components such as central processing units (CPUs) and related products for business and consumer markets. Intel was the world's third-largest semiconductor chip manufacturer by revenue in 2024 and has been included in the Fortune 500 list of the largest United States corporations by revenue since 2007. It was one of the first companies listed on Nasdaq.","{\"organizationType\":\"COMMERCIAL\"}","graphrag,graphrag,openalex","2026-06-02T23:34:17.641337022","2026-07-27T08:24:14.132390683","companyType","COMPANY","foundedDate","1968-07-18","headquarters","Santa Clara","country","United States","employeeCount",121100,"fundingStage","totalFunding","valuation","website","https://www.intel.com","stockSymbol","uscc","crunchbaseUrl","Intel (United Kingdom)","英特尔","Intel Corporation","Intel (United States)","Intel (India)",{"_15":164,"_29":165,"_31":-5,"_32":-5,"_33":-5,"_34":-5,"_35":36,"_37":166,"_39":-5,"_40":41,"_42":167,"_44":168,"_142":169,"_144":-5,"_145":170,"_48":165,"_147":171,"_149":172,"_151":173,"_153":174,"_52":175,"_156":-5,"_157":176,"_159":-5,"_160":86,"_58":165,"_59":-5},{"_15":137,"_29":138,"_31":-5,"_32":-5,"_33":-5,"_34":-5,"_35":36,"_37":139,"_39":-5,"_40":41,"_42":140,"_44":141,"_142":143,"_144":-5,"_145":146,"_48":138,"_147":148,"_149":150,"_151":152,"_153":154,"_52":155,"_156":-5,"_157":158,"_159":-5,"_160":86,"_58":138,"_59":-5},"paper_W2015917466","A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance","{\"openalex\":\"W2015917466\",\"doi\":\"10.1109/jssc.2010.2089657\"}","2026-05-22T03:59:51.458116451","2026-05-22T03:59:51.458118336","doi","10.1109/jssc.2010.2089657","arxivId","openalexId","W2015917466","abstractText","A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to mitigate the clock frequency (F _CLK ) guardbands for dynamic parameter variations to improve throughput and energy efficiency. The core supports two distinct error-detection designs, allowing a direct comparison of the relative trade-offs. The first design embeds error-detection sequential (EDS) circuits in critical paths to detect late timing transitions. In addition to reducing the Fclk guardbands for dynamic variations, the embedded EDS design can exploit path-activation rates to operate the microprocessor faster than infrequently-activated critical paths. The second error-detection design offers a less-intrusive approach for dynamic timing-error detection by placing a tunable replica circuit (TRC) per pipeline stage to monitor worst-case delays. Although the TRCs require a delay guardband to ensure the TRC delay is always slower than critical-path delays, the TRC design captures most of the benefits from the embedded EDS design with less implementation overhead. Furthermore, while core min-delay constraints limit the potential benefits of the embedded EDS design, a salient advantage of the TRC design is the ability to detect a wider range of dynamic delay variation, as demonstrated through low supply voltage (V _CC ) measurements. Both error-detection designs interface with error-recovery techniques, enabling the detection and correction of timing errors from fast-changing variations such as high-frequency V _CC droops. The microprocessor core also supports two separate error-recovery techniques to guarantee correct execution even if dynamic variations persist. The first technique requires clock control to replay errant instructions at 1/2F _CLK . In comparison, the second technique is a new multiple-issue instruction replay design that corrects errant instructions with a lower performance penalty and without requiring clock control. Silicon measurements demonstrate that resilient circuits enable a 41% throughput gain at equal energy or a 22% energy reduction at equal throughput, as compared to a conventional design when executing a benchmark program with a 10% V _CC droop. In addition, the microprocessor includes a new adaptive clock control circuit that interfaces with the resilient circuits and a phase-locked loop (PLL) to track recovery cycles and adapt to persistent errors by dynamically changing Fclk f°Γ maximum efficiency.","publishedDate","2010-12-10","publishedYear",2010,"venue","IEEE Journal of Solid-State Circuits",264,"authors","keywords",[161,162,163],"pdfUrl","topVenue","Low-power high-performance VLSI design","VLSI and Analog Circuit Testing","Radiation Effects in Electronics","paper_W2096927458","Characterization of soft errors caused by single event upsets in CMOS processes","{\"openalex\":\"W2096927458\",\"doi\":\"10.1109/tdsc.2004.14\"}","2026-05-15T21:19:04.219015981","2026-05-21T16:09:05.192687868","10.1109/tdsc.2004.14","W2096927458","Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. 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Tanay Karnik 人物

Tanay Karnik · 相关专利