A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation 论文
1998IEEE Transactions on Electron Devices引用 330
VLSI and Analog Circuit TestingVLSI and FPGA Design TechniquesLow-power high-performance VLSI design
详细信息
- 发表期刊/会议
- IEEE Transactions on Electron Devices
- 发表日期
- 1998-03-01
- 发表年份
- 1998
关键词
VLSI and Analog Circuit TestingVLSI and FPGA Design TechniquesLow-power high-performance VLSI design
摘要
Based on Rent's Rule, a well-established empirical relationship, a rigorous derivation of a complete wire-length distribution for on-chip random logic networks is performed. This distribution is compared to actual wire-length distributions for modern microprocessors, and a methodology to calculate the wire-length distribution for future gigascale integration (GSI) products is proposed.