Upset hardened memory design for submicron CMOS technology 论文
1996IEEE Transactions on Nuclear Science引用 1143
Radiation Effects in ElectronicsVLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure Analysis
摘要
A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using submicron CMOS technology.