Automatic symbolic verification of embedded systems 论文

1996IEEE Transactions on Software Engineering引用 491
Formal Methods in VerificationEmbedded Systems Design TechniquesReal-Time Systems Scheduling

详细信息

发表期刊/会议
IEEE Transactions on Software Engineering
发表日期
1996-03-01
发表年份
1996

关键词

Formal Methods in VerificationEmbedded Systems Design TechniquesReal-Time Systems Scheduling

摘要

Presents a model-checking procedure and its implementation for the automatic verification of embedded systems. The system components are described as hybrid automata-communicating machines with finite control and real-valued variables that represent continuous environment parameters such as time, pressure and temperature. The system requirements are specified in a temporal logic with stop-watches, and verified by symbolic fixpoint computation. The verification procedure-implemented in the Cornell Hybrid Technology tool, HyTech-applies to hybrid automata whose continuous dynamics is governed by linear constraints on the variables and their derivatives. We illustrate the method and the tool by checking safety, liveness, time-bounded and duration requirements of digital controllers, schedulers and distributed algorithms.