An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS 论文
2007Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference引用 634
Interconnection Networks and SystemsLow-power high-performance VLSI designParallel Computing and Optimization Techniques
摘要
A 275mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-F04 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.