An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS 论文

2007Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference引用 634
DOI
Interconnection Networks and SystemsLow-power high-performance VLSI designParallel Computing and Optimization Techniques
Parallel Computing and Optimization TechniquesLow-power high-performance VLSI designInterconnection Networks and Systems
相关技术:Interconnection Networks and SystemsParallel Computing and Optimization Techniques
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An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS · 相关技术

相关技术

Interconnection Networks and SystemsParallel Computing and Optimization Techniques