Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes 论文

2003IEEE Transactions on Computers引用 229
DOI
VLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure AnalysisVLSI and FPGA Design Techniques
半导体VLSI and FPGA Design TechniquesVLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure Analysis
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Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes · 作者

K

Krishnendu Chakrabarty

A

Anshuman Chandra