Embedded deterministic test for low cost manufacturing test 论文

2003引用 401
VLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure AnalysisEngineering and Test Systems

摘要

This paper introduces embedded deterministic test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.

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