A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations 论文
2008IEEE Journal of Solid-State Circuits引用 261
Physical Unclonable Functions (PUFs) and Hardware SecurityIntegrated Circuits and Semiconductor Failure AnalysisVLSI and Analog Circuit Testing
详细信息
- 发表期刊/会议
- IEEE Journal of Solid-State Circuits
- 发表日期
- 2008-01-01
- 发表年份
- 2008
关键词
Physical Unclonable Functions (PUFs) and Hardware SecurityIntegrated Circuits and Semiconductor Failure AnalysisVLSI and Analog Circuit Testing
摘要
A 128-bit, 1.6 pJ/bit, 96% stable chip ID generation circuit utilizing process variations is designed in a 0.13 mum CMOS process. The circuit consumes 162 nW from a 1 V supply at low readout frequencies and 1.6 muW at 1 Mb/s. Cross-coupled logic gates were employed to simultaneously generate, amplify, and digitize the random circuit offset to create a stable unique digital chip ID code. A thorough statistical analysis is presented in order to explore the ID circuit reliability and stability. Two ID generators with different layout techniques were designed and fabricated to provide a performance comparison of power consumption, ID stability, and ID statistical robustness.