An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS 论文

2008IEEE Journal of Solid-State Circuits引用 627
DOI
Interconnection Networks and SystemsParallel Computing and Optimization TechniquesEmbedded Systems Design Techniques
Parallel Computing and Optimization TechniquesEmbedded Systems Design TechniquesInterconnection Networks and Systems
相关技术:Parallel Computing and Optimization TechniquesInterconnection Networks and Systems
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An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS · 作者

S

Shekhar Borkar

N

Nitin Borkar

Y

Yatin Hoskote

C

Clark Roberts

V

Vasantha Erraguntla

S

Shailendra Jain

T

Tiju Jacob

A

A. Singh

D

D. Finan

J

James Tschanz

H

H. Wilson

S

Saurabh Dighe

G

Greg Ruhl

J

Jason Howard

S

Sriram Vangal