Knights Landing: Second-Generation Intel Xeon Phi Product 论文

2016IEEE Micro引用 443
Semiconductor materials and devices3D IC and TSV technologiesParallel Computing and Optimization Techniques

详细信息

发表期刊/会议
IEEE Micro
发表日期
2016-03-01
发表年份
2016

关键词

Semiconductor materials and devices3D IC and TSV technologiesParallel Computing and Optimization Techniques

摘要

This article describes the architecture of Knights Landing, the second-generation Intel Xeon Phi product family, which targets high-performance computing and other highly parallel workloads. It provides a significant increase in scalar and vector performance and a big boost in memory bandwidth compared to the prior generation, called Knights Corner. Knights Landing is a self-booting, standard CPU that is completely binary compatible with prior Intel Xeon processors and is capable of running all legacy workloads unmodified. Its innovations include a core optimized for power efficiency, a 512-bit vector instruction set, a memory architecture comprising two types of memory for high bandwidth and large capacity, a high-bandwidth on-die interconnect, and an integrated on-package network fabric. These features enable the Knights Landing processor to provide significant performance improvement for computationally intensive and bandwidth-bound workloads while still providing good performance on unoptimized legacy workloads, without requiring any special way of programming other than the standard CPU programming model.